Modern mobile devices continue to demand an increasing amount of operating time from a single battery charge. Accordingly, power management is a primary concern for many mobile device manufacturers. One major source of power consumption within a mobile device is the power amplifier used in the transmission of wireless signals. A well designed power amplifier may reduce the power requirements of the mobile device in which it is incorporated, thereby significantly extending the battery life of the mobile device.
FIG. 1 shows conventional single-ended power amplifier circuitry 10 for use in a mobile device. The conventional single-ended power amplifier circuitry 10 includes an amplifying transistor 12 including a collector contact 14, an emitter contact 16, and a base contact 18, biasing circuitry 20, an input capacitor 22, an output capacitor 24, and an output inductor 26. The base contact 18 of the amplifying transistor 12 is coupled to the biasing circuitry 20. The input capacitor 22 is coupled between the base contact 18 of the amplifying transistor 12 and an input terminal 28. The emitter contact 16 of the amplifying transistor 12 is coupled to ground. The collector contact 14 of the amplifying transistor 12 is coupled to a supply voltage VCC through the output inductor 26. The output capacitor 24 is coupled between an output terminal 30 and the collector contact 14 of the amplifying transistor 12.
The conventional single-ended power amplifier circuitry 10 is adapted to receive an input signal V_INPUT at the input terminal 28 and produce at the output terminal 30 an amplified output signal V_OUTPUT. Although the conventional single-ended power amplifier circuitry 10 effectively amplifies the input signal V_INPUT, the circuitry suffers from a relatively low efficiency when compared to alternative power amplifier architectures. Due to the limited output voltage of the conventional single-ended power amplifier circuitry 10, the output impedance of the conventional single-ended power amplifier circuitry 10 must be kept low, on the order of 2-3Ω for a power delivery of 2 W with a supply voltage VCC of 3.6 V and a saturation voltage of 100 mV. In order to match the low output impedance of the conventional single-ended power amplifier circuitry 10 with a load, the output capacitor 24 and the output inductor 26 are adapted to match the impedance of the load. Assuming a standard load impedance of 50Ω, the transformation ratio of the output capacitor 24 and the output inductor 26 should be around 16. Because of the relatively high transformation ratio required by the conventional single-ended power amplifier circuitry 10, the efficiency of the circuitry will suffer, thereby degrading the performance of a mobile device in which the conventional single-ended power amplifier circuitry 10 is incorporated.
One way to increase the efficiency of a power amplifier is to use a differential architecture. FIG. 2 shows conventional differential power amplifier circuitry 32 for use in a mobile device. The conventional differential power amplifier circuitry 32 includes a differential transistor pair 34 including a first transistor TR1 and a second transistor TR2, an input transformer 36, an output transformer 38, and biasing circuitry 40. The input transformer 36 includes a single-ended input terminal 42, a first differential output terminal 44, and a second differential output terminal 46. The input transformer 36 is adapted to receive a single-ended input at the single-ended input terminal 42, and produce a differential output signal at the first differential output terminal 44 and the second differential output terminal 46. The output transformer 38 includes a first differential input terminal 54, a second differential input terminal 56, and a single-ended output terminal 50. The output terminal is adapted to receive a differential input signal at a first differential input terminal 54 and a second differential input terminal 56, and produce a single-ended output signal at the single-ended output terminal 50.
The first transistor TR1 includes a collector contact 52, an emitter contact 58, and a base contact 60. The collector contact 52 of the first transistor TR1 is coupled to the first differential input terminal 54 of the output transformer 38. The emitter contact 58 of the first transistor TR1 is coupled to ground. The base contact 60 of the first transistor TR1 is coupled to the first differential output terminal 44 of the input transformer 36. The second transistor TR2 also includes a collector contact 62, an emitter contact 64, and a base contact 66. The collector contact 62 of the second transistor TR2 is coupled to the second differential input terminal 56 of the output transformer 38. The emitter contact 64 of the second transistor TR2 is coupled to ground. The base contact 66 of the second transistor TR2 is coupled to the second differential output terminal 46 of the input transformer 36. The biasing circuitry 40 is coupled at the midpoint of the differential output terminals 44 and 46 of the input transformer 36.
The conventional differential power amplifier circuitry 32 is adapted to receive an input signal V_INPUT at the single-ended input terminal 42 of the input transformer 36, and produce at the single-ended output terminal 50 of the output transformer 38 an amplified output signal V_OUTPUT. Due to the differential architecture of the conventional differential power amplifier circuitry 32, the amplified output signal V_OUTPUT is increased by a factor of two over the conventional single-ended power amplifier circuitry 10. Accordingly, the output impedance of the differential transistor pair 34 can be about four times higher than that of the conventional single-ended power amplifier circuitry 10 while maintaining substantially the same power output. As a result of the increased output impedance of the conventional differential power amplifier circuitry 32, the transformation ratio of the output transformer 38 is reduced by a factor of four, resulting in a higher efficiency than what is achievable by the conventional single-ended power amplifier circuitry 10 shown in FIG. 1.
Although the conventional differential power amplifier circuitry 32 is capable of efficiently producing an amplified output signal V_OUTPUT from an input signal V_INPUT, the conventional differential power amplifier circuitry 32 may suffer from instability due to the high gain characteristics of the differential transistor pair 34 at low frequencies. Accordingly, a power amplifier is needed that is both efficient and stable in order to increase the operating time of a mobile device in which it is incorporated.